1. 28 Jun, 2019 2 commits
  2. 27 Jun, 2019 3 commits
  3. 26 Jun, 2019 5 commits
  4. 25 Jun, 2019 1 commit
  5. 24 Jun, 2019 10 commits
  6. 23 Jun, 2019 4 commits
    • Noah Misch's avatar
      Don't call PG_RETURN_BOOL() in a function not returning Datum. · 9a81c9fa
      Noah Misch authored
      This code is new in v12, and the defect probably was not user-visible.
      9a81c9fa
    • Dean Rasheed's avatar
      Add security checks to the multivariate MCV estimation code. · d7f8d26d
      Dean Rasheed authored
      The multivariate MCV estimation code may run user-defined operators on
      the values in the MCV list, which means that those operators may
      potentially leak the values from the MCV list. Guard against leaking
      data to unprivileged users by checking that the user has SELECT
      privileges on the table or all of the columns referred to by the
      statistics.
      
      Additionally, if there are any securityQuals on the RTE (either due to
      RLS policies on the table, or accessing the table via a security
      barrier view), not all rows may be visible to the current user, even
      if they have table or column privileges. Thus we further insist that
      the operator be leakproof in this case.
      
      Dean Rasheed, reviewed by Tomas Vondra.
      
      Discussion: https://postgr.es/m/CAEZATCUhT9rt7Ui=Vdx4N==VV5XOK5dsXfnGgVOz_JhAicB=ZA@mail.gmail.com
      d7f8d26d
    • Thomas Munro's avatar
      89ff7c08
    • Tom Lane's avatar
      Fix spinlock assembly code for MIPS so it works on MIPS r6. · 1323bfce
      Tom Lane authored
      Original MIPS-I processors didn't have the LL/SC instructions (nor any
      other userland synchronization primitive).  If the build toolchain
      targets that ISA variant by default, as an astonishingly large fraction
      of MIPS platforms still do, the assembler won't take LL/SC without
      coercion in the form of a ".set mips2" instruction.  But we issued that
      unconditionally, making it an ISA downgrade for chips later than MIPS2.
      That breaks things for the latest MIPS r6 ISA, which encodes these
      instructions differently.  Adjust the code so we don't change ISA level
      if it's >= 2.
      
      Note that this patch doesn't change what happens on an actual MIPS-I
      processor: either the kernel will emulate these instructions
      transparently, or you'll get a SIGILL failure.  That tradeoff seemed
      fine in 2002 when this code was added (cf 3cbe6b24), and it's even
      more so today when MIPS-I is basically extinct.  But let's add a
      comment about that.
      
      YunQiang Su (with cosmetic adjustments by me).  Back-patch to all
      supported branches.
      
      Discussion: https://postgr.es/m/15844-8f62fe7e163939b3@postgresql.org
      1323bfce
  7. 22 Jun, 2019 1 commit
  8. 20 Jun, 2019 3 commits
  9. 19 Jun, 2019 11 commits